Rambus uses the Avery HBM3 memory model to verify its PHY subsystem and HBM3 controller
Tewksbury, MA – December 8, 2021 – Avery Design Systems, a leader in functional verification solutions, today announced full support for the new HBM3 interface standard. Rambus uses Avery’s high-quality HBM3 memory models to verify the new Rambus HBM3 memory subsystem.
The Rambus HBM3 memory subsystem, consisting of an HBM3 PHY and HBM3 controller, is optimized for systems that require a high bandwidth, low latency memory solution. This includes applications in AI / ML training, graphics, and high performance computing (HPC). The subsystem supports data rates up to 8.4 Gbps per data pin and has 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this provides a total interface bandwidth of 1075.2 GB / s.
Rambus uses Avery’s full high-quality memory model to verify its HBM3 PHY and controller. Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP. Customers can then license the Avery memory models for use in the full SoC audit.
âWe deliver fully integrated and verified memory subsystems to meet the time to market and quality requirements of our customers. Avery is a trusted partner and plays a vital role in helping us ensure that our memory subsystems perform as promised, âsaid Brian Daellenbach, Senior Director of Memory & MIPI Controllers, IP Interface at Rambus.
Avery offers a comprehensive functional verification platform based on its robust Verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its HBM3 offering includes memory models, protocol verifiers, performance analyzes and compliance test suites using a flexible and open architecture. HBM2E and HBM3 speed adapters are also available for FPGA prototyping platforms.
âOur mutual customers need quick access to verified models of the latest standards, as well as a verification platform to enable a reliable verification methodology. Our collaboration with Rambus allows developers to stay ahead of the curve as new standards emerge. We are excited to be able to provide an HBM3 verification solution, which enables our customer to confidently develop compute-intensive SoCs in advanced processes, âsaid Chris Browy, vice president of sales / marketing at Avery.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables systems design and SOC teams to dramatically improve functional verification productivity through the use of formal analysis applications for verification of X-level pessimism. of the gate and the actual root cause X and the sequential backtracing; and robust chip-level verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI / DSI, I3C, DDR / LPDDR, HBM, ONFI / Toggle / NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD / SDIO, CAN FD and FlexRay. The company has established numerous affiliations of the Avery Design VIP Partner Program with major IP vendors. More information about the company can be found at www.avery-design.com.