Cadence DRAM Verification Solution Optimizes SoC Designs for Data Center and Automotive Applications


Cadence Design Systems announced a new DRAM verification solution, enabling customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications.

Using the full DRAM verification solution, which provides up to 10x higher verification throughput, customers can perform IP-level verification at SoCs of advanced designs with multiple DDR interfaces.

Modern SoC designs take advantage of advanced memory technologies, such as LPDDR5x, DDR5, HBM3 and GDDR6, which require rigorous verification at the PHY and IP levels to ensure compliance with the JEDEC standard as well as verification at the SoC level to meet application-specific system performance definitions. and data and cache coherency requirements.

“DRAM memory verification requires unique methods to ensure that all timing, power and throughput requirements are met under various conditions,” said Paul Cunningham, senior vice president and general manager, R&D, System Group and Cadence verification. “With the industry’s first comprehensive DRAM verification solution, we enable our customers to efficiently verify their IP designs and ensure that their designs comply with the JEDEC standard specification as well as the application-specific performance metrics of the memory subsystem to provide the fastest path to IP and system verification shutdown.”

The new DRAM verification solution enables IP-level verification through Cadence PHY VIPs and memory models with a direct and transparent path to SoC-level verification with the Cadence System VIP solution, including System Performance Analyzer, system traffic libraries and system dashboard, all with built-in integration and content for DRAM interfaces, enabling fast and efficient verification of the memory subsystem and SoC for simulation and emulation environments.

The solution also includes Cadence TripleCheck technology, which provides users with a specification-linked verification plan, including JEDEC, DFI and PHY, comprehensive coverage models and a test suite to ensure compliance with the interface specification. .

“Micron is committed to leading the development of next-generation memory technologies that drive value from the data center to the intelligent edge and across customer and mobile user experiences,” said Malcolm Humphrey, vice president and director general manager of the Compute DRAM product group at Micron. “Our collaboration with Cadence accelerates the development of the ecosystem to deliver innovative memory solutions.”

The new verification solution for DRAM verification is part of the broader Cadence full verification workflow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, Jasper formal verification platform, virtual studio and hybrid Helium and vManager verification management platform.

Cadence’s comprehensive review stream delivers the highest throughput of bug reviews per dollar invested per day. The DRAM verification solution and complete verification flow support the company’s intelligent system design strategy, enabling excellence in SoC design.


About Author

Comments are closed.