European-designed RISC-V chip comes to life – Bulk Solids Handling

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THE’ PEV Where European Transformers Initiative aims to allow the design in Europe of components intended for high performance computing and supercomputers.

No longer wanting to lag behind other geographical areas with only partial access to the latest technologies, and therefore with a strategic and economic disadvantage, a consortium was formed to create the necessary chips that will allow Europe to get back into the HPC computing race ( High performance computing ).

Part of this strategy will involve the development of components leveraging the open architecture RISC-V . A first chip EPAC (for European processor accelerator ) was therefore designed with this in mind.

PPE EPAC RISC V

After the design was announced in June, the first EPAC 1.0 test chips have been manufactured and PPE approved to verify proper operation.

143 test chips were thus produced by GlobalFoundries using its 22 FDX etching technique with 22 x 22 FCBGA package for an operating rate of 1 GHz.

PPE EPAC RISC V 02

PPE EPAC chip awakening

EPAC is an accelerator combining different elements provided by European companies. It consists of four blocks comprising an Avispado RISC-V kernel from SemiDynamics and a VPU (Vector Processing Unit) designed by the BSC (Barcelona Supercomputing Center) and the University of Zagreb.

There is also a memory subsystem and several STX accelerators ( Stencil / Tensor Accelerator ) and VRP ( Precision processor variable ), the latter coming from CEA LIST, the whole being connected in the chip by a high-speed NoC (Network on Chip) and a SerDes from Extoll.

The EPAC chip should make it possible to validate a certain number of intellectual property blocks in the design of the RISC-V chips which will serve as the basis for a European HPC ecosystem.

The next generation of chip will move to 03nm with performance improvements and low power consumption, as well as on a chip design.


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