European Processor Initiative EPAC1.0 RISC-V Test Chip Samples delivered


September 22, 2021 – The European Processor Initiative (EPI), a project with 28 partners from 10 European countries, with the aim of making the EU independent in HPC chip technologies and HPC infrastructure, is proud to announce that EPAC1.0 RISC- Samples of V test chips have been delivered to EPI and the first tests of their functioning have been conclusive.

One of the key segments of EPI’s business is to develop and demonstrate processor IPs fully developed in Europe and based on the RISC-V instruction set architecture, providing high performance accelerator cores and low energy consumption known as EPACs (European Processor Accelerators).

EPAC combines several specialized accelerator technologies for different fields of application. The test chip, shown in the figure below, contains four vector processing micro-tiles (VPUs) consisting of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by the Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed by Chalmers and FORTH respectively, which provide a consistent view of the memory subsystem. The chip also includes two additional accelerators: the Stencil and Tensor (STX) accelerator designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) from CEA LIST. All of the on-chip accelerators are connected to a very high-speed on-chip network and to EXTOLL’s SERDES technology.

All 143 packaged EPAC test chip samples were manufactured with GLOBALFOUNDRIES 22FDX low power technology, have an area of ​​26.97mm2, 14 million placeable instances (93M Gate Equivalent) including 991 memory instances, are packaged in FCBGA with 22 × 22 balls and have a target frequency of 1 GHz.

Figure 1: EPAC test samples
Figure 2: Hello everyone! screenshot

The initial setup was successful and EPAC performed their first bare metal program sending out the traditional “Hello World!” greetings in different languages ​​to the EPI consortia and to the world!


EPI will continue to develop, optimize and validate different IP blocks and demonstrate the characteristics and performance of those that thus create an EU HPC IP ecosystem and make it available to the processor and accelerator industry and universities for create globally competitive production class building blocks for next generation HPC systems.

Source: European Transformers Initiative


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