European supercomputer project receives RISC-V test chips


The EPI project has 28 partners from 10 European countries, with the aim of enabling the EU to achieve independence in HPC chip technologies and HPC infrastructure. 43 of the EPAC1.0 RISC-V test chips were delivered to EPI by GlobalFoundries and the first tests of their functioning were conclusive.

The European Processor Accelerator (EPAC) combines several specialized accelerator technologies for different application areas. Built in a 22nm process, the 1GHz chips have a surface area of ​​26.97mm2 with 14 million placeable instances, or the equivalent of 93m of gates, including 991 memory instances.

The test chip contains four vector processing micro-tiles (VPUs) consisting of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by the Barcelona Supercomputing Center and the University of Zagreb.

Each tile also contains a Home Node and L2 cache, designed by Chalmers and FORTH respectively, to provide a consistent view of the memory subsystem.

The chip also includes two additional accelerators: the Stencil and Tensor (STX) accelerator designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) from CEA LIST. All on-chip accelerators are connected to a very high-speed network-on-chip and EXTOLL’s SERDES technology.

The chips were made in GF’s 22FDX low power technology and are packaged in FCBGA with 22 × 22 balls

The initial setup was successful and EPAC performed its first bare metal program sending out the traditional “Hello World!” greetings in different languages ​​to the EPI consortia and to the world!

EPI says that it will continue to develop, optimize and validate different IP blocks and demonstrate the functionality and performance of these thus creating an EU HPC IP ecosystem and making it available to the processor and processor industry. accelerators and universities for next generation HPC systems.

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