The development cycle of an integrated circuit (IC) –– or informally, of a chip –– from the conceptual phase to production and shipping to end users involves several stages. One metric to measure cycle length is time to market (TTM) which stops when the chip leaves the factory. The absence of TTM is a terrible event that can jeopardize the success of the chip and possibly the future of the business. Adhering to the TTM schedule also does not guarantee a revenue stream from its sale. This metric is known as access time (TTE). Even if the TTM is on schedule, missing the TTE can cause serious problems for the seller.
Consider the case of a systems company purchasing a batch of chips and subjecting them to an inbound inspection. If the inspection fails, no income would be paid to the seller. If the inspection passes, but the chip fails in the field once installed in a product, the relationship between supplier and customer would be compromised forever.
Extensive IC testing before shipping can be a challenge for TTM but helps TTE.
Recent statistics reveal that the cost of testing a batch of chips after manufacture to determine which parts are free from manufacturing defects (as opposed to free from design bugs) adds up to 40% to the cost of building the chip.
Each of these considerations is driving the electronics industry to devise methods to build testability into the chip at the design stage to reduce testing costs and increase product quality.
The methodology that makes this possible is known as Design for Testability (DFT) and can:
- Ensure detection of all faults in a circuit to increase product quality and speed up TTE
- Reduce cost and time associated with test development to improve manufacturing economies and accelerate TTM
- Decrease the execution time of fabricated chip tests, speeding up TTM
The DFT is usually incorporated into the door-level design after it has been verified to be functionally correct before registering the netlist at the foundry. Unfortunately, inserting the on-chip test infrastructure can compromise its functional integrity, making it essential to perform gate-level verification of the design after DFT implantation. The size of the netlist after insertion increases dramatically, extending the verification time far beyond an already compressed TTM schedule.
Given the level of complexity of the design, the door-level simulation –– the traditional benchmark verification tool –– would require many months, if not years, for a thorough and complete verification. Instead, this task is a perfect match for a hardware emulation platform. Only hardware emulation can verify the functionality of the chip, regardless of its size and complexity, with a capacity of over a billion ASIC gates, operating at a speed several orders of magnitude faster than simulation. While all hardware emulators today support the speed and capacity of work, only custom silicon-based emulators provide 100% visibility of every node in the design needed for failure analysis.
Emulation with a DFT application
A new DFT “app” is available for hardware emulation to fully verify a Design Under Test (DUT) that includes DFT implemented into an already constrained schedule. It makes two changes to using a hardware emulator –– a change in the build flow and a change in execution at run time.
First, the hardware emulation compiler reads a design at the instrumented gate with the DFT structure as well as a file in IEEE Standard Test Interface Language (STIL) format including the design I / O configuration, clock information and test vectors. The compiler creates an infrastructure to read the test vectors from the STIL file.
While hardware emulation operates at a speed that is several orders of magnitude faster than simulation, the DFT application checks DFT models by four or five orders of magnitude. Concretely, three months of simulation, or 2,160 hours, can be accomplished in less than an hour.
|DFT (design for testability) application offers performance advantages over traditional simulation.|
A hardware emulator provides enough power to keep the DFT verification schedule on track, increasing throughput and speeding up both TTM and TTE, thus increasing profits. It expands the use model of hardware emulation, improves performance, and helps a verification engineer to avoid risk and ensure the quality of chips delivered to customers.
Dr Lauro Rizzatti ([email protected]) is a verification consultant and industry expert in hardware emulation. He has held positions in management, product marketing, technical marketing and engineering.