Intel introduces Sapphire Rapids multi-chip processor with HBM


Intel has officially confirmed that some “Sapphire Rapids” 4th Generation Xeon Scalable processors will include onboard HBM memory late last year, but the company has never demonstrated an actual processor equipped with HBM or revealed its DRAM configuration. At the International Microelectronics Symposium hosted by IMAPS earlier this week, the company finally presented the processor with HBM and confirmed its multi-chip design.

While Intel has confirmed many times that Sapphire Rapids processors will support HBM (likely HBM2E) and DDR5 memory and can use HBM with or without main DDR5 memory, it never featured a real processor equipped with HBM, until this week (thanks to the photo posted by Tom Wassick /@wassickt).

It turns out that each of the four Sapphire Rapids chips has two HBM memory stacks that use two 1024-bit interfaces (i.e. a 2048-bit memory bus). Formally, JEDEC’s HBM2E specification achieves a data transfer rate of 3.2 GT / s, but last year SK Hynix began mass-producing 16 GB 1024 pin stacked arrays (KGSD) rated for 3.6 GT / s operation.

If Intel chooses to use such KGSDs, HBM2E memory will provide the Sapphire Rapids processor with a maximum memory bandwidth of 3.68 TB / s (or 921.6 GB / s per die), but only for 128 GB of memory. In contrast, SPR’s eight channels of DDR5-4800 memory supporting one module per channel and offering 307.2 GB / s will support at least 4 TB of memory using Samsung’s recently announced 512 GB DDR5 RDIMMs. .

It’s also worth noting that Sapphire Rapids equipped with HBM come in a large BGA form factor and will be soldered directly to the motherboard. This is not particularly surprising since Intel’s LGA4677 form factor is quite narrow and the processor does not have enough space on its case for HBM batteries.

Additionally, processors that require a very high performance memory subsystem like HBM tend to have loads of cores that run at high frequencies and have a very high TDP. Keeping in mind that HBM batteries are also power hungry, it might not be easy to develop an outlet that would power a beast equipped with HBM. Therefore, it looks like SPRs equipped with HBM will only be offered to certain customers (just like Intel Xeon Scalable 9200 processors with up to 56 cores) and will be primarily for supercomputers.

Another thing to note is that the shape of the SPR chips in the image is rectangular rather than square (like the early images of Sapphire Rapids in the LGA4677 package). The author of the image said it was from an Intel graphic “donated by an Intel employee and labeled SPR, and verbally noted as Sapphire Rapids.” That said, it looks like the Sapphire Rapids processor supporting HBM may have a different chip configuration than traditional SPR processors (ultimately, traditional Xeon Scalable processors don’t need an HBM interface that supports space on the chip).

Intel’s Sapphire Rapids processors will include a host of new technologies including support for PCIe Gen 5 with CXL 1.1 protocol for accelerators, a hybrid memory subsystem supporting DDR5 and HBM, advanced matrix expansions Intel (AMX) as well as the AVX512_BF16 and AVX512_VP2INTERSECT instructions designed for data center and supercomputer workloads, and Intel Data Streaming Accelerator (DSA) technology, to name a few.

Earlier this year, we learned that Intel’s Sapphire Rapids uses a multi-chip package with EMIB interconnects between the chips, unlike its predecessors which are monolithic. Although the number of cores depends on performance and horsepower (some reports say that SPR will have up to 56 active cores, but actual chips can hold up to 80 cores), it’s obvious that the 4th Gen Xeon Scalable will be the first to use the latest packaging technologies and Intel’s design paradigm.


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