Minimal RISC-V


Microcontrollers exist in almost everything, but can RISC-V meet the needs of this market? Is it small enough to replace 8-bit processors? What could help people migrate to a more modern processor architecture?

RISC-V defines a 32-bit processor instruction set architecture (ISA) that is open source and free to be implemented in multiple ways. It is presented as a very small and efficient architecture, and at the same time has been defined to be easily extensible. Many add-ons are already approved extensions, and many were unveiled at the RISC-V Summit in December 2021.

But questions remain. Is the base spec small enough? Instead of adding additional functionality, is it necessary to remove elements? Is it useful as a microcontroller? The 8-bit microcontroller market was around $8 billion in 2020, and is expected to grow between 4% and 5% in the foreseeable future, according to several industry reports. In 2014, 8-bit was still the largest volume, accounting for 39.7% of sales, while 32-bit followed closely at 38.5%.

Today, the 16-bit market has become the largest, with a 48.8% share. 8-bit is gradually losing market share, but this is moving to 16-bit and not necessarily 32-bit. Most of them are discrete chips, and there is clearly a large and sustainable market for small processors.

Controllers everywhere
Complex devices may contain a number of controllers, but they rarely attract attention. “There are many chips with multiple large Arm cores used as an applications processor, but you’ll also find many much smaller processors there,” says Simon Davidmann, CEO of Imperas Software. “They’re used to do all sorts of things, and a lot of them might just be niche RISC-V-based processors. Nobody really knows what they are, because they’re hidden away.

And these processors are not bound by the same rules. “You will always have a few processors doing the general processing and orchestrating the movement of data in a system,” says Michael Frank, colleague and system architect at Arteris IP. “They do everything that needs to be Turing-complete and programmable. But then you have a few things that are specialized. And that’s the best use of the silicon area, because now you can leave out anything you don’t need in the algorithm.

Other major markets for microcontrollers include automotive, HVAC, IoT, and medical. A RISC-V core can take as few as 20,000 gates, so why would anyone bother trying to optimize it further, when it’s likely that an entire chip could have millions of gates ? In some cases, cost is the most critical element, which means the smallest area possible. For others, it’s power. For devices that are expected to last months or years on a single battery, any logic of doing nothing is considered wasteful and needs to be eliminated.

Minimal RISC-V
The RISC-V base is small. It contains only 47 instructions that everyone must implement. This compares to 1,503 for an x86 and around 500 for Arm. It uses the simplest load/store architecture, which means that all operations are performed on internal registers and there are dedicated instructions for transfer between registers and memory.

“RISC-V starts with a simple integer instruction set, basically the bare bones of a processor already,” says Frank of Arteris. “There’s not much you can get out of it. The simplest RISC-V processor implementation has 32-bit integers. That’s what a microcontroller used to be. I don’t see why you would want to strip it down further. The Berkeley team has created a beautiful layered and scalable architecture. They learned from everything they had done before and building a number of variations and extensions built into the architecture, I would still consider this a base layer rather than something that can be cut.

In the instruction set it is possible to set the size of the register file. “A very interesting aspect of RISC-V is that you can scale it down,” says Davidmann of Imperas. “What RISC-V is trying to do, as an organization, is help people do things like this. For example, there is the E version which reduces the number of registers. It’s usually 32, but this version only defines 16.”

For example, SiFive recently discussed an implementation of the RV32E that can be configured to be implemented in just 13,500 gates. ZERO-RISCY, a kernel developed as part of the PULP platform for power-efficient computing, has a two-stage pipeline implementation that consumes 11,600 gates.

The spec also allows simple controllers to be defined that don’t require a lot of logic to sit around the core. “They tried to make it so that you could even design it without the privilege mode capabilities and the control/status registers, so you could reduce it to a really simple controller,” says Davidmann. “It still lets you use standard assembler, and it’s still RISC-V, but it’s not going to do your floating point very quickly. It’s just a very small controller.

Some of these reductions are due to early work on the standard. “There can be many reasons why it would be useful to drop a large design to get a smaller processor,” says Ashish Darbari, Founder and CEO of Axiomise. “There are already examples of publicly available processors. For example, ZERO-RISCY and Ibex, two RISC-V cores from the PULP Platform group, are scaled-down versions of RI5CY that later became cv32e40p. In this specific case, RI5CY had custom instructions that were not part of the RISC-V ISA standard.

One reduction that does not seem to be contemplated concerns the size of the words. “If you reduce the word size, you lose the capability and the beauty of the RISC-V processor, where you can do address calculations, integer calculations, all in the same registers, in the same ALUs”, explains Frank. “It’s very hard to keep anything useful after you remove RISC-V. The beauty of RISC-V is that there’s a tool chain, and if you start cutting things out, you’re on your own.

Ironically, an extension can generate savings. “If you have multiple processors on a chip, each of them can be optimized or customized for specific tasks,” says Zdeněk Přikryl, CTO at Codasip. “It could be AI, it could be security, it could be anything. We allow processors to be designed in a high-level architecture description language, by which we capture the instruction set, which could be called the architecture view, as well as the microarchitecture view, which is basically the implementation of the ISA. Since we have this unique description in a high-level architecture language, we are able to generate the compilers, assemblers, disassemblers, simulators, and ultimately the RTL.

One of these extensions is the compressed instruction set, which reduces code space. Compressed instructions allow you to put two instructions into a single 32-bit word. This reduces the amount of program memory required, although it adds very slightly to processor complexity. One claim is that it takes 400 gates to implement this. This is probably more than offset by the reduction in memory area. Other attempts to do this, such as the Arm Thumb format, are essentially a different instruction set.

Thus, an optimized core does not always imply the smallest. “We had a client who started investigating ratified extensions of RISC-V extensions, trying to find the best compromise,” says Codasip’s Přikryl. “They started with the baseline, then added extensions and looked at combinations of different extensions. They looked at not only performance, but also size and memory footprint. One of the key things is that the processor is part of a system and you are trying to optimize that system, in this case it was important to have efficient code because when you implement a subsystem in silicon, your instruction memory is l “one of the major consumers of energy and power. We managed to reduce the code size by a factor of about three during this optimization.”

Making changes brings some complexity into the process. “Anyone can take RISC-V and make changes to it,” says Davidmann. “They can add pieces, take the ones they like and throw away the ones they don’t like. As long as it’s for a deeply integrated system, nobody cares what they end up with. No one will ever see it. And that’s why, in the beginning, no one really cared about compatibility and compliance. “

Modified kernels should be verified. “The biggest challenge down this path is figuring out what the delta changes are doing to the overall functionality of the core, as well as figuring out that the delta is doing what it’s supposed to do,” says Axiomise’s Darbari. “These are strengths for formal methods that can find deviations by checking the architectural conformance of the reduced kernel against a set of architectural properties formally specified in formalISA, an application for formally verifying RISC-V cores.”

The RISC-V ISA as specified is a minimal but complete processor architecture that can be implemented in less than 20,000 gates. The standard has taken into account that in some cases only a minimal kernel is required and variants and extensions have been defined to make it adaptable to issues such as code size. Extensions can produce more optimal cores that not only get the job done faster, but can also reduce size, power, or other aspects that are important in a particular application.

In the words of John Lydgate, later adapted by President Lincoln, “You can please some people all the time, you can please everyone once in a while, but you can’t please everyone.” the weather.”

RISC-V International has done a pretty good job of keeping most people happy.

Working with RISC-V
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RISC-V Knowledge Center
Top RISC-V stories, videos, white papers and blogs.
High Level Synthesis for RISC-V
Abstraction is key to designing and verifying custom processors, but defining the right language and tool flow is a work in progress.
RISC-V targets data centers
Open source architecture is gaining traction in more complex designs as the ecosystem matures.
RISC-V Verification Challenge Propagation
Ongoing design innovation is adding to the complexity of verification and driving more companies to do so.


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