A new tool claims to identify and correct traceability gaps between disparate systems such as requirements, specifications, EDA tool sets, software code, and documentation in systems-on-a-chip (SoC) designs. This allows chip designers to know immediately when a change is occurring and its effect on other design artifacts and parts of the system.
Harmony Trace, implemented as an enterprise-level server application with a web user interface (UI), facilitates full visibility of requirements traceability throughout the SoC design flow and product lifecycle. In addition, it facilitates compliance with functional safety and quality standards such as ISO 26262, IEC 61508, ISO 9001 and IATF 16949.
Figure 1 Harmony Trace automates SoC design traceability by interfacing with EDA, documentation, existing requirements, software engineering, and support systems. Source: Arteris IP
A complex SoC often involves a suite of disparate and disconnected tools. So, as the SoC goes through the lifecycle of its product, design engineers have to manage the entire lifecycle. “This makes it difficult to trace design requirements and artifacts throughout the SoC lifecycle,” said Mike Demler, senior analyst at The Linley Group. “Harmony Trace alleviates these issues by connecting discrete silos, allowing users to track requirements, implementation, verification, and documentation inconsistencies between existing systems. “
It also means SoC designers can continue to use EDA and other tools like IBM DOORS, Jama, Jira, DITA, and IP-XACT. “Harmony Trace establishes an automated traceability flow and implements change management among requirements, specifications, EDA, code repository and documentation tools,” said K. Charles Janac, President and CEO from Arteris IP.
The tool shows how Arteris and Magillem technologies have merged to follow all SoC requirements and follow them throughout the design process. Arteris acquired Magillem in November 2020 and made it the company’s IP deployment division. “Our network-on-a-chip (NoC) interconnects need the information from every IP block attached to it in order to configure it properly,” said Kurt Shuler, vice president of marketing at Arteris IP. “Magillem creates this information for each IP block. “
As a result, there is automatic connectivity of IP blocks based on Magillem’s IP-XACT metadata.
Figure 2 Harmony Trace offers automatic IP block connectivity based on XACT IP metadata. Source: Arteris IP
Paul Graykowski, Senior Technical Marketing Director at Artris IP, explained the reasoning in more detail. “There are a lot of IPs going into an SoC, and we interconnect them using NoC technology,” he said. “For that, we need information relating to these different blocks, and this is where Magillem technology comes in. The IP-XACT model provides all the configuration information to assemble the chip.
We have all of this metadata to automate much of the topology synthesis workflow, Graykowski added. Thus, engineers can perform many optimizations for power, performance and area (PPA), memory management and control of software interfaces. “This is how we will put everything together without having to re-enter information at each stage of the creation of the SoC. “
Traceability in SoC design
When it comes to SoC design, it all starts with requirements that translate into architecture. The architects hand it over to the design team, who develop the specifications and begin to implement that design with coding. Coding is followed by some basic testing at the subsystem level, and after that the integration tasks are done in conjunction with the hardware and software teams.
Finally, you find yourself in the acceptance phase, where high-level checks make sure the chip has met its goals and documents are released. However, each of these phases described above has its own controls in place. So if something in verification is discovered, the engineers go back to the design committee, which has an impact on the requirements.
Here’s the catch; design engineers must trace these impacts.
It should be mentioned that each of these phases uses its own tools. If you are working with requirements, it is likely that you are using IBM DOORS. These requirements need to be translated into a real architecture because the tools don’t speak, and then this needs to be translated on the design side, starting with HDL coding and running simulations.
But each of these phases has a flaw. So a person takes the information and translates it into a data source. However, the tools in these phases don’t talk to each other, so you need to fine-tune all of that. And if you’re missing something in all of these loopholes, what happens is when you have silicon internally, you find out that you have an issue that violates a requirement. As a result, you may have to re-spin the chip, which is very expensive.
figure 3 Harmony Trace collects, maintains and reports information moving through different SoC building blocks. Source: Arteris IP
“That’s where Harmony Trace comes in,” Graykowski said. The tool aims to bring it all together, so if something changes along the way, SoC designers immediately know that a specific requirement has been violated. “Harmony Trace links all of these systems together, creating one big system where everything is talked about,” he added. “There is complete visibility into everything that changes, and engineers can react to that change in real time and correct it so that it doesn’t become a costly problem down the road. “
Key features of the traceability tool
When it comes to Harmony Trace’s unique features, the first thing is that while it consolidates items into one system, users don’t have to modify their existing feeds. They can continue to use tools, such as IBM DOORS and Jira, that they already use. Harmony Trace connects these tools through a single process, thus filling the gaps in these systems. The user logs in through a web browser and can interact with how requirements relate to artifacts and monitor violations.
So, if something downstream changes and violates the requirements, it is identified, and then human interaction can occur to resolve that issue.
In addition, the tool supports industry standards such as ISO 26262, IEC 61508, ISO 9001 and IATF 16949. This, among other things, speeds up functional safety assessments by identifying and correcting traceability deviations. between disparate systems.
Another thing that Harmony Trace offers is the built-in reporting. Right now, engineers do their engineering work while tracking things and creating reports, which are either used for design review or for certification and safety audits. “It’s a lot of time and effort, and it’s not always done the same,” Graykowski noted.
He added that with Harmony Trace, all information flowing between the different systems is collected, stored and reported. Design engineers can get the report with one click, take that report, and work with their peers on design reviews or safety audits. It makes their life much easier.
More traceability features
Harmony Trace captures the design history and all of this information is stored in the tool and can be easily output. The tool offers four to five types of reports, and they are available in PDF, Word, and Excel formats. A multi-page report is typically 38 to 40 pages long.
Then there’s the traceability matrix, a color-coded spreadsheet; on one port there are all the requirements, and on the other port it has all the artifacts for the requirements. The matrix shows how they are related and if they are related. Harmony Trace also has a built-in API that allows engineers to customize the report. They can also edit it if they need it in a particular format.
“The main advantage of Harmony Trace is that every requirement is followed and downstream changes are identified,” Graykowski concluded. “When they change and violate the requirement, a review process is triggered.”