Siemens Emulation and Prototyping Tools Solve SoC Design Challenges


Article by: Majeed Ahmad

A Cohesive System takes hardware, software and system verification to the next level of emulation and prototyping platform innovation.

The success of a system-on-a-chip (SoC) design is increasingly tied to software performance, making it essential to bridge the gap between the hardware and software development workflows. It is therefore not surprising that this era of software-centric SoC designs imposes dramatic changes in functional verification systems in the field of integrated circuit design.

Modern SoCs feature multi-billion-door designs, and their size and complexity keep growing. More importantly, while software performance determines SoC performance, long software runs require extended check cycles. Additionally, SoC designers are increasingly using software workloads and benchmarks to verify power and performance.

MLPerf for AI chips and AnTuTu for mobile chips are an example. Accurate power and performance analysis during bench and workload cycles requires visibility into power activity, precise analysis, and comprehensive debugging tools. Siemens Digital Industries Software aims to solve this semiconductor mega-cycle design conundrum with a new generation of verification solutions by creating a comprehensive suite of emulation and prototyping tools.

[Download Report] Imagine the future of electronics

According to Jean-Marie Brunet, senior director of product management and engineering for emulation and prototyping at Siemens EDA, the company has expanded its Veloce product family, formerly known as the Veloce emulator, to create a complete story. Here are the highlights of this design story.

The right tool for the right task

SoC designers should look at the analysis of power and performance, then run workloads, frameworks, and benchmarks to see how the SoC behaves from a power and performance perspective. According to Brunet, this requires a hybrid system that has all of the key elements of the engineer’s verification toolbox.

“We now have all the pieces of the puzzle: the HYCON virtual platform, the Strato + emulator providing full chip visibility and versatility in the FPGA prototyping space with the Primo and proFPGA platforms,” ​​said Brunet by summarizing the complete suite of emulation and prototyping. tools that encompass large hardware enclosures, office equipment and software platforms.

Veloce HYCON

A virtual platform for software-driven verification, Veloce HYCON provides the pre-silicon view of the SoC, including validation and characterization of the software workload. It decouples software dependencies from hardware development and software validation begins immediately.

“In a hybrid environment, SoC designers have less content on RTL and more content on the virtual model, and as a result, they can run software at hundreds of MIPS with the virtualized environment,” Brunet said. He added that HYCON is the only solution on the market that enables early analysis of software workload while being integrated into a hardware-assisted verification platform.

Additionally, after maximizing verification cycles, SoC designers can transition on the fly from this virtualized hybrid environment to an emulation platform that meets the hardware team’s need for precision. And that brings us to the hardware emulator: Veloce Strato +.

Veloce Strato +

A capacity upgrade to the Veloce Strato hardware emulator launched in 2017, Veloce Strato + helps SoC developers meet designs of over 10 million doors, up to 15 million doors. “It offers a 1.5x capacity enhancement that runs on the same chassis and facilitates risk-free, push-button migration,” Brunet said.

He added that improving performance comes down to three things: compile, run, and debug. Strato + uses a distributed architecture to take advantage of repetitive hierarchical designs and thus speed up compilation time. Then, it improves execution time with faster throughput and facilitates faster debugging with 100% visibility.

AMD’s second and third generation EPYC processors have been qualified for use with the Veloce Strato and Veloce Strato + platforms. “When you are testing a chip of this size, improving capacity is essential,” Brunet said.

Veloce Primo

When RTL reaches a level of stability, where debugging is less critical and performance is more important, IC designers can offload emulator tasks to an enterprise FPGA prototyping platform. “Now it’s all about speed and the need to run 5-10 times faster than an emulator,” Brunet said.

Veloce Primo, an enterprise FPGA prototyping platform, offers much-needed scalability with a design capacity of up to 320 FPGAs. At the same time, it is consistent with the Veloce Strato platform with the same RTL, software workload, compiler model and virtual environment.

Veloce proFPGA

Unlike Veloce Primo, intended for large parameters like the data center, Veloce proFPGA handles smaller capacities with individual access. “The footprint and size fit on a desk, typically in the lab, in a point-to-point setting for one user at a time,” Brunet said. On the other hand, Veloce Primo offers rack-based enterprise access with multiple chassis and much faster.

Veloce proFPGA is a modular system based on high-end FPGAs like Intel Stratix 10 GX 10M and Xilinx XCVU19P. Siemens EDA also announced that it has signed an OEM agreement for desktop prototyping with Pro Design.

All the pieces of the IC design puzzle

If SoC designers go straight to prototyping, when the RTL is not debugged, they must debug it in the prototyping engine. “Good luck because the prototype is not a debugging environment; it’s an environment conducive to speed, ”Brunet warned.

Nonetheless, the gradual transition from an emulator to a prototype enterprise environment is crucial, Brunet pointed out. Laurie Balch, Research Director at Pedestal Research, recognizes that having an integrated suite of tools is valuable because it allows design teams to tackle a range of verification challenges from different angles without having to tinker with piecemeal solutions. stroke.

She added that delivering high capacity and configurability is how Strato + and HYCON are targeting the next generation of increasingly dense, gate-counting SoCs that require advanced emulation and prototyping tools right from the start. stages of the design cycle. “The model of hardware and software engineers operating in separate silos is no longer feasible. “

This means that the hardware must know the software, and the software must know the hardware early in the design process. To do this, says Siemens EDA, it has created a comprehensive suite of emulation and prototyping tools that encompass large hardware enclosures, office equipment, and software platforms.

This article was originally published on EE time.

Majeed Ahmad, Editor-in-Chief of Electronic Design News (EDN), has covered the electronics design industry for more than two decades. He holds a master’s degree in telecommunications engineering from the Eindhoven University of Technology. He has held various editorial positions, including assignments for EE Times Asia and Electronic Products.


About Author

Leave A Reply