Sifive Essential 6-Series RISC-V processors target Linux, real-time applications

SiFive has been busy. Just days after the announcement of SiFive Performance P650, the company announced the SiFive Essential 6-Series RISC-V processor family starting with four 64-bit / 32-bit real-time cores and two Linux-compatible application cores, plus the SiFive Version 21G3 with various improvements to existing families.

SiFive Essential 6-Series line of RISC-V processors

The Essential 6-Seris family is made up of three sub-families with two processors each:

• E6 Series with 1.91 DMIPS / MHz, 3.69 CoreMark / MHz
  • E61-MC – 32-bit quad-core onboard processor
  • E61 – Mid-range performance 32-bit on-board processor (one core)
• S6 series with 2.07 DMIPS / MHz, 3.73 CoreMark / MHz
  • S61-MC – 64-bit quad-core onboard processor
  • S61 – Mid-range performance 64-bit embedded processor (one core)
• U6 Series with 2.07 DMIPS / MHz, 3.73 CoreMark / MHz
  • U64-MC – Quad-Core 64-Bit Application Processor
  • U64 – Linux-compatible midrange processor (one core)

The E6 and S6 series real-time processors have virtually the same specifications, except for 32-bit and 64-bit cores, and a different number of interrupts.

• Fully compliant with the RISC-V ISA specification
  • Up to four 32-bit RV32Is (E6 series) or 64-bit RV64I (S6 series) RISC-V kernels
  • Machine and user mode support
  • 8-step pipeline, unique number and in order
• Advanced memory subsystem
  • 16 KB, bidirectional instruction cache
  • Tight Integrated Instruction Memory (ITIM) option
  • Up to 64KB Data Tightly Integrated Memory (DTIM) support
• Efficient and flexible interruptions
  • Local interrupts with vectorized addresses – up to 16
  • Platform Level Interrupt Controller (PLIC)
    • E6 series – 128 interrupts with 7 priority levels
    • S6 series – 511 interrupts with 7 priority levels
  • RISC-V main local switch (CLINT) – 1 timer, 1 software
• 8-region physical memory protection (PMP)
• High performance AMBA interfaces
• Detailed Power, Performance and Area (PPA) Info – SiFive will only tell you by email …

Highlights of the U6 series application processors:

• Fully compliant with the RISC-V ISA specification
• Up to four 64-bit RISC-V application cores
  • 32KB I-cache L1 with ECC
  • 32 KB L1 D-cache with ECC
  • 8-region physical memory protection
  • Support for virtual memory with up to 47 physical address bits
  • 128KB L2 cache integrated with ECC
• Real-time capabilities
  • L2 cache can be configured in deterministic high speed SRAMs
• CLINT for multicore timer and software interrupts
• PLIC with support for up to 128 interrupts with 7 priority levels – Debugging with instruction trace
• Detailed Power, Performance and Area (PPA) information – Again, no luck unless you contact SiFive directly

The Essential 6-Series is essentially the mid-range equivalent of the high-end SiFive 7 Series processors. Further details can be found on the SiFive Essential page.

SiFive says the E6 series is equivalent to the Arm Cortex-M0, M0 +, M3, M4, M23, and M33 cores, a fairly wide range, but they haven’t listed any Arm Cortex equivalent for the S6 and U6 series.

SiFive 21G3 version

In addition to the new RISC-V cores, SiFive also announced version 21G3 with improved clock synchronization and power management, SiFive Shield WorldGuard support for the Essential family, and the SiFive Performance family now includes RISC-V Hypervisor extension, as discussed in the recent Performance P650 kernel announcement. SiFive Intelligence Extensions found in SiFive Intelligence X280, add support for BFLOAT16 compute, quantization acceleration and get better multi-cluster support to improve performance of learning workloads Automatique.

Jean-Luc started CNX Software in 2010 part-time, before stepping down as head of software engineering and starting writing daily news and reviews full-time later in 2011.